Three of the major trends in semiconductor packaging are efforts to shrink the package outline so that the package consumes less area and less height when it is mounted onto the circuit board, and to reach these goals with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called "chip-scale packages". These packages have an outline adding less than 20% to the chip area; however, their height has not yet reached the desired low profile, and their cost is too high relative to the chip cost. In addition, some of the designs and processes being investigated have a detrimental effect on the overall device reliability. A chip-scale package which has only the size of the chip itself, is often referred to as "chip-size package".
Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called "board-on-chip" design. Recently, patent application serial # 9702348-5 entitled "Board on Chip--Ball Grid Array Chip Size Package" has been filed by Texas Instruments in Singapore on Jul. 2, 1997. This patent application for memory products successfully approaches the problems of reducing the area requirement by replacing the traditional leaded package design with a solder ball concept, and of reducing the height requirement by replacing the leadframe-on-chip assembly with a board-on-chip design. However, some frustrating problems remain unresolved: Gold wires in bonding assembly have to span high loops over metal lines on the board--since they must avoid accidental touching which would cause electrical shorts--which, in turn, limits the chance of reducing the package height. Or otherwise cumbersome and expensice insulation has to be applied over the metal lines to prevent electrical shorts to the gold wires.
Furthermore, if the process of wire bonding is to be executed using installed conventional bonder equipment, electrical grounding of the device is required in order to close an electrical control circuit involving the bonder as well as the bond-to-be made and to insure defect-free bonding quality. As long as metallic leadframes are being used, this requirement is no issue, but it becomes a problem when boards, films or flexible printed circuits made of insulating material are used. Proposed solutions employing needle-like movable probes are cumbersome for mass production. A more elegant and low cost design solution is desirable.
Consequently, a need has arisen for package designs and methods of device fabrication that provide simplified, low-cost processes resulting in simplified and more reliable products, and at the same time achieve improvements towards the goal of small outline and low profile packages. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.